1. Field of the Invention
The present invention relates to a method for forming an isolation layer in a semiconductor device, and more particularly to a method for forming an isolation layer using epitaxial silicon growth.
2. Description of the Prior Art
In general, as the degree of integration in semiconductor devices becomes higher and higher, new research is conducted into an isolation process using trench etching and chemical mechanical polishing (CMP) processes instead of the existing local oxidation of silicon (LOCOS).
One embodiment of a method for forming an isolation layer according to the prior art will be described below in reference with FIGS. 1 and 2.
First, as shown in FIG. 1, a pad oxide layer 2 and a nitride layer 3 are formed in turn on a silicon substrate 1, and then patterned together in a predetermined size to expose the silicon substrate 1. The exposed silicon substrate 1 is etched to form a trench.
Subsequently, as shown in FIG. 2, the trench formed in the silicon substrate 1 is filled with an oxide layer 4. The resulting structure is, in turn, subjected to a CMP process, a cleaning process, and a formation process of a sacrificial oxide layer.
However, in the method for forming a trench isolation layer as mentioned above, the oxide layer filled into the trench has a cutout edge A, a so-called trench edge, due to an anisotropy of the oxide layer. This trench edge causes various remnants to remain therein during etching of a word-line, which hinders the device from operating stably. Due to a fringing electric field generated at the trench edge, a transistor hump takes place, and thereby increasing a sub-threshold current In addition, an inverse narrow width effect is generated to deteriorate a property of the device.
Another embodiment of a method for solving these problems by forming an isolation layer according to the prior art is shown in FIGS. 3 to 5.
First, referring to FIG. 3, a pad oxide layer 12 and a nitride layer 13 are formed in turn on a silicon substrate 11, and then patterned together in a predetermined size to expose the silicon substrate 11. The exposed silicon substrate 11 is etched to form a trench. In this case, the silicon substrate 11 is etched in a step shape using remnants generated during a formation of the trench in the silicon substrate 11.
Then, as shown in FIG. 4, an oxidation process is preformed to form an oxide layer 14, by which a corner of the trench of the silicon substrate 11 is rounded off.
Subsequently, as shown in FIG. 5, the trench is filled with an oxide layer 15. The resulting structure is subjected to a CMP, and thus an isolation layer with a round profile is formed along the edge of the trench.
In contrast, another conventional method is dependent on a pattern size. Specifically, it is easy for a wide pattern to form such a step, while it is difficult for a narrow pattern such as in a highly integrated dynamic random access memory (DRAM) to form such a step. Therefore, there is a high possibility of the generation of defects, for example, the cutout edge A of the oxide layer may cause an electric property of the device to deteriorate. Further, when the trench is formed, a change in the step shape depending on the pattern size has an influence on an electric property of the device. Moreover, there is a problem in that when the trench is formed, a thermal oxide layer is formed to remove the cutout oxide layer and to round off the corner of the trench, and then a sacrificial oxidation process is performed to remove the thermal oxide layer, the corner of the trench becomes weaker.
Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and an object of the present invention is to provide a method for forming an isolation layer in a semiconductor device using an etching process for forming a trench, in which no loss is generated at a corner of an isolation insulation layer filled into the trench, and no remnant is generated in the following process, thereby obtaining a stable electric property of the device.
Another object of the present invention is to provide a method for forming an isolation layer in a semiconductor device, in which when a masking insulation layer and an isolation oxide layer are sequentially subjected to a dry etching process in accordance with an isolation mask pattern, the isolation oxide layer is etched to have a thickness within hundreds of angstroms from the top surface of the silicon substrate, thereby preventing the silicon substrate from being damaged by plasma. Therefore, reliability of the device can be improved.
To accomplish these objects, there is provided a method for forming an isolation layer in a semiconductor device, comprising the steps of;
forming in turn an isolation oxide layer, a masking insulation layer and a mask pattern on an silicon substrate;
etching the masking insulation layer and then the isolation oxide layer in part by a dry etching process in accordance with the mask pattern, the isolation oxide layer being etched to have a predetermined thickness;
removing the mask pattern and then completely removing the isolation oxide layer having a predetermined thickness on the silicon substrate to form a trench; and
growing an epitaxial silicon layer on the resultant to form an epitaxial silicon active area.